There is a well known strong drive for designers to shrink dimensions of CMOS integrated circuits. The advantages of smaller dimensions include:
more logic gates per area (i.e. more functionality)
lower power per gate (which scales with area)
faster device speed, hence faster overall circuit speed
lower manufacturing cost per function.
These strong advantages will continue to drive a need to shrink dimensions. At the present time, virtually all semiconductor manufacturing use optical lithographic methods, with exposure wavelengths as short as 193 nm.
As dimensions in integrated circuits have shrunk down to the limits of resolution of current lithographic technology, many attempts have been made to circumvent the resolution limitations of optical lithography. These novel lithographic approaches include:
X-ray lithography with wavelength of approximately 1 nm.
Since no lenses are available for this wavelength, simple proximity printing is used which means that the mask pattern is the same size as the desired wafer pattern.
The extremely fine patterns on a thin membrane mask were found to be extremely difficult to fabricate, with resultant high defect rates and high cost.
E-beam lithography has very short wavelength and potentially very high resolution. Unfortunately, it is very difficult to get high throughput out of such tools. Low throughput, as is well known, requires more tools to maintain a desired production, with an increased capital cost that is reflected in an increased wafer cost.
Projection lithography with wavelengths shorter than 193 nm, such as 157 nm or EUV wavelengths, can have improved resolution over current tools. Unfortunately, the cost of using such technology is so high that it is not clear whether they can be used in production in the foreseeable future.
In summary, each of these novel lithography approaches has failed to deliver a manufacturing solution with acceptable overall cost.
A completely different approach to getting an improved pattern is to use multiple exposures of current lithographic technology to achieve higher resolution. In recent years, there has been a lot of work in this area.
The first example of such an approach is the use of an alternating Phase Shift Mask in combination with a Trim mask, as described in a recent paper [M. Kling et al., “Practicing extension of 248 DUV optical lithography using trim-mask PSM”, SPIE 3679, pp. 10-17 (1999)]. Here a single layer of photoresist is exposed twice, once with an alternating phase shift mask (PSM) and then with a Trim mask. After the double exposure, the pattern is developed out by normal lithographic processing. The second exposure by the Trim mask serves to remove unwanted image artifacts from the PSM. It is important to note that when using double exposure into a single layer of photoresist, that the normal spatial frequency limits of optical lithography remain in place, i.e. it is not possible to double the resolution with this technique.
A second example of double exposure where it is possible to double the resolution has been described in S. R. J. Brueck, [“There are no fundamental limits to optical lithography”, pp. 85-109 (Chapter 5) of International Trends in Applied Optics, edited by A. H. Guenther, SPIE Press, 2002].
It is important to note that in this processing sequence, two layers of resist are independently patterned, and therefore it is possible to double the spatial frequency of the pattern. In their example, one layer of a bi-layer resist is exposed with a 1:3 line space pattern and then, after the first pattern is developed, a buffer layer to cover the topography from the first resist and, a new layer of resist is added. The pattern is then shifted by half the pitch and the new layer of resist is exposed. The level of the imaging surface has been raised by the new material, so the focus plane must be adjusted appropriately. At the conclusion of the resist patterning, the two sets of developed resist structures are used as masks to pattern the target film. The main emphasis of this work is to achieve patterns with doubled density over the single exposure method. This paper offers useful tools for patterning the mask and performing the etching, but is limited to two separate patterns that do not interact.
In current technology, a CMOS device is built up from a number of pattern layers, most of which are not relevant to the current invention. One of the most critical pattern layers that is important to the present invention defines the transistor gates, and because this layer is typically made of a polysilicon material, the layer is usually called the “Poly” pattern. In future processes, the polysilicon material might be replaced by new materials such as silicides or metals, and this invention may readily be extended to apply our methods to these gate patterns. The quality of the Poly pattern is crucial to high speed devices, and this invention will show how to define patterns with superior quality.
In order to express the problem addressed by this invention, we consider only three of the many levels of this CMOS circuit: Poly, Active Area, and Contact Hole. These levels will be quite familiar to those skilled in the art of CMOS circuit design. Different portions of the Poly pattern perform different functions. The “poly gate” area is defined as those poly lines which cross the “active area” level and thereby form a transistor. The “poly interconnect” area comprises the poly lines which are outside the active area, and simply serve as conductive wires. The “contact landing pad” area is normally somewhat wider than the interconnect and gate lines, since a separate contact hole pattern must land on this pad, even in the presence of some overlay error between the contact and the poly pattern.
It is well known that control of the “poly gate” area is crucial to the attainment of high speed circuitry. In particular, linewidth deviations of the gates will cause transistor speed deviations which will disrupt the desired overall circuit timing and performance.
One of the most difficult parts of the poly gate to control is the region near a contact pad. FIG. 1 illustrates this problem, with FIG. 1A showing an idealized design and FIG. 1B showing the actual dimensions that result from diffraction. Poly line 100 extends left-right in FIG. 1A in an idealized figure having a linewidth denoted by line 12. The actual poly gate linewidth shown in FIG. 1B is considerably larger in the area near the landing pad, essentially because of the inability to print a sharp corner. Line 112 in FIG. 1B is considerably larger than the idealized line 12 in FIG. 1A.
One simple way of reducing this problem is to move the contact landing pad away from the active area, so that the poly line is under good control by the time it becomes a gate. But this solution is very expensive, because it increases the size of the circuit, and when repeated for the millions of gates of a VLSI circuit will cause a significant increase in chip size. The increased chip size is more costly for two reasons: the number of chips per wafer will go down and the larger chip will be more susceptible to defects on the wafer.
The present invention will disclose methods to shrink CMOS designs by use of a novel double exposure method which will directly address the problem of gate linewidth variation.